Lakhs of Base DRC at Floorplan/Placement database | Physical Verification | Interview Question

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Lakhs of Base DRC at Floorplan/Placement database:


Let's say you are working on one of the complex blocks of chip designing and you are responsible for closing the Place-and-Route (PnR) activity of the design. You are responsible for doing floor-planning, placement, clock tree synthesis, routing, and signoff activities. Floorplan is one of the most important tasks in physical design activities. One of the major tasks in floor-planning is macro placement, identification, and creation of physical power domains based on UPF, doing power planning including placement of physical cells like tap cells, boundary cells, power switches, guard rings, marker cells, and a few others.


Let's say you completed the floor-planning and are ready to go for placement. Before going to the placement run, have you done sanity checks to ensure that your floorplan is completely clean and okay? For a sanity check with respect to physical violations, don't consider timing as of now to limit the discussion of this topic. You can check short/DRC in physical tools like Fusion Compiler, Innovus, and fix it, and then go for placement. Is it enough? Let's assume you ran placement and did standard cell filler insertion and ran signoff DRC, and you get lakhs of base DRC. What may be wrong here?


To cross-verify the floorplan database, you can do standard cell filler insertion, and ran signoff DRC, and still, you are getting lakhs of base DRC. What is wrong here? What type of base DRC can you expect at floorplan? What type of base DRC at floorplan is okay to proceed to placement? What kind of base DRC at floorplan is not okay to proceed to placement and requires immediate fix?


I'll keep an eye out for the answers. Feel free to share them, and I'll be happy to discuss or provide further insights.


Answer will be updated here soon.


Happy Learning! 


#scripting #coding #Tcl #pd #physicaldesign #physicalverification #pv #vlsi #design #india #semiconductor #freshers #professional #hardware #floorplanning #motivation #leadership #magnet #bound #placement #synopsys #cadence #interview #vlsi #question #longer #routing #longnet #delay #timing #rc #resistance #capacitance #basedrc



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