Placement | Physical Design | Congestion / Power / Area Setup | Part 3

By


Dear Readers,

In our previous vlogs, we looked into the fundamentals of placement flow and algorithms, as well as the general setup mandatory for placement runs.

Below are the links to access these blogs :

Placement - Part 1

https://compile-vlsi.blogspot.com/2024/03/understanding-of-placement-physical.html

Placement - Part 2

https://compile-vlsi.blogspot.com/2024/03/placement-physical-design-part-2.html


    In today's vlog, let's explore congestion and power/area-driven setup for placement runs.

    1. 1. Congestion Effort Level:

    Low/medium/high/ultra effort levels could be set for global routing during placement. A low effort level is recommended for the initial run to achieve faster runtime. After the initial placement run, analyze the congestion. If the congestion overflow is high or borderline, rerun placement with a higher effort level.

    route_global -congestion_map_only true -effort_level high

    Apart from the global route effort level, we can also adjust the placement effort level of different placement stages to a higher effort level.

    place_opt.initial_place.effort high

    place_opt.final_place.effort high


    2.Keepout Margin (Halo):

    Ensure that a keep-out margin has been applied to macros/memory.

    create_keepout_margin 


    2. 3.Placement Blockage:

    Create necessary placement blockages in areas prone to congestion.

    create_placement_blockage


    1. 4.Cell density/Pin density:

    Congestion could occur due to high cell/pin density. Control the cell/pin density in prone areas using partial blockage. Alternatively, define an overall density percentage.

    create_placement_blockage -type partial -blocked_percentage 40 -boundary <>

    place.coarse.pin_density_aware

    place.legalize.optimize_pin_access_using_cell_spacing

    (The above command will improve the routability of areas with high pin density by redistributing the cells.) 


    1. 5. Congestion Driven Restructuring (CDR):

    Cells with high pin density, like AOI/OAI, could cause many net crossings, creating congestion hotspots.

    CDR setup identifies these, reorders, and places them optimally, reducing wirelength and alleviating congestion.

    place.coarse.cong_restruct

    place.coarse.cong_restruct_effort


    Power and Area Setup:

    1. 1.Effort level:

    We can set effort levels for power and area. The tool will use available algorithms to reduce power and area by default.

    opt.power.effort -value high

    opt.area.effort -value high

    The above settings may reduce area/power at the cost of timing degradation. 


    1. 2.Pre-Route Layer Optimization:

    This setting automatically assigns longer and more timing-critical nets to higher layers. With this setting, the number of buffers required for the same path may be reduced.

    place_opt.flow.optimize_layers -value true


    2. 3.Low Power Placement:

    Low-power placement requires a switching activity file. This setting will reduce dynamic power by shortening high-activity nets.

    place.coarse.low_power_placement -value true

    read_saif <>

    The switching activity file can be read using the above command.


    These are the basic setup requirements for congestion and power/area. Let's look into timing-driven setup in the next vlogs.


    Happy learning!


    #physicaldesign #vlsi #india #infineon #semiconductor #physicalverification #timing #sta #design #learning #development #jobs #freshers


    Comments

    Post a Comment

    Must Read

    Understanding of Placement (Physical Design) - Part 1

    By
    In physical design, following floor-planning, the crucial step is placement, which heavily relies on the quality of the floorplan. Today, let's delve into placement algorithms. Before commencing placement, conducting necessary checks called pre-placement checks is imperative. To ensure better timing quality, the following steps must be completed before initiating placement: 1.Physical synthesis must be completed. so we can use coarse placement in placement stage.       2. EDA tool offers command to check for pre-placement issue. >check_design -checks pre_placement_stage (synopsys command) >check_design -type place -out_file pre_place_checks.tcl (cadence command) The above commands examine issues related to placement such as PG DRC, PG missing via, pin placement, grid, feedthrough issues, etc. Running these commands before placement aids in identifying major issues that could impede the placement process. Different stages for the placement run ...
    Read more

    Interview Question - Physical Design (PD) | Clock Skew

    By
      Interview Question (PD): Consider a design that has undergone floor-planning, placement, Clock Tree Synthesis (CTS), and routing, complete Physical Design (PD) activity. After multiple iterations to fix timing, two runs have been generated: Run A with zero skew (practically not possible, but assume) and Run B with a skew of 50ps. Both runs meet the required timing specifications. Which run is the good one? Can we go ahead with the zero skew run, or should we opt for the run with some skew? What are the disadvantages of going with the zero skew run? In particular, are there any potential issues with the zero skew run that could lead to reliability or performance problems down the line? For example, might the zero skew run be more sensitive to process, voltage, and temperature (PVT) variations, IR drop or more prone to clock signal degradation? On the other hand, does the run with some skew provide a more realistic and robust clock distribution network that can better withstand va...
    Read more

    Dealing with Congestion in a Practical Way (Physical Design) :

    By
    Dealing with Congestion in a Practical Way (Physical Design): Simply put, if number of required track is more than available track in a specific GRC, the tool flags an overflow in that area. The tool breaks down the chip core into small GRCs (Global Route Cells) and assesses overflow, reporting it for horizontal, vertical, and both layers. Normally, the overflow percentage should stay below 1%, requiring analysis if it exceeds that. But what if it's significantly high, like 10-20%? Even with a high overflow, the tool routes, but at the expense of shorts and DRC violations, resulting in poor net quality. Long nets contribute to high RC values, causing more delays and eventually timing violations in design. Therefore, prioritizing congestion analysis is crucial. Let's look into potential causes of congestion/overflow: 1.Improper logic optimization during synthesis. 2.Bad floorplan (Check my post on floorplan for macro placements). https://lnkd.in/gU9PnZve 3.Incorrect standard ce...
    Read more

    Scripting Interview Question | Physical Design | VLSI

    By
    Scripting Interview Question Role: Physical Design Company : Product Based Experience: 5+ years Write a program or suggest an algorithm that compares two files containing lines of code. The program should perform the following tasks: Consider all possible solutions and identify the most efficient one. Identify and report matching patterns between the two files. Identify and report non-matching patterns between the two files. Propose a solution for scenarios where the file sizes are small (hundreds of lines of code). Propose a solution for scenarios where the file sizes are large (thousands of lines of code). Discuss whether the same solution works for both small and large file sizes. Instructions for Submission: Please post your answers in the comment section below. For detailed explanations and solutions, check the answers later on compile-vlsi.blogspot.com Answer: (Updated on 01 Aug 2024) Approach 1: Brute Force Description: Use two nested loops to compare each line of the first f...
    Read more

    LVS Issue | Physical verification | VLSI

    By
    In Physical Design Verification / Layout Verification, one crucial process to ensure the manufacturability of chips is Layout vs Schematic (LVS). While other checks such as DRC, Antenna and Density issues are relatively easier to handle through scripting and custom approaches, LVS demands careful analysis and debugging. In Simple word, LVS involves comparing the source netlist, which can be generated from a Verilog netlist (.v file) using v2lvs, with the layout netlist extracted from GDSII/Oasis files (.gds /.oas). To ensure a smooth verification process and to get LVS smiley, certain tips should be followed: Clean up open and short connections during the routing stage and fix any hierarchical shorts if detected. Power-related shorts and opens can be identified separately by running soft-check and ERC on the layout. Ensure that the Base DRC is free from issues. Legalization problems like overlaps, missing fillers, or tap cells can lead to unnecessary LVS discrepancies. When generating ...
    Read more

    Port Punching | Physical Design | VLSI

    By
    Image
    Port Punching in Physical Design VLSI: Port punching refers to the process where a synthesis or implementation tool automatically creates a port to facilitate connections between hierarchical levels. Let's understand this with a simple example. During the power planning stage, we use UPF commands like create_supply_net, create_supply_port, and connect_supply_net. These commands facilitate the addition of ports between hierarchical levels to establish supply connections, ensuring proper power distribution across the design. Another example is feedthrough port punching/creation. In multi-voltage domains, many nets need to travel long distances due to multiple power domains. Since nets are not permitted to cross voltage areas to which they do not belong, this can lead to excessive wiring, congestion, and potential timing violations. We can address these issues by breaking these nets using feedthroughs with extra ports created on the voltage area boundary, allowing nets to travel into ...
    Read more

    Low Power Design | Physical Design | Part 1

    By
    Low Power Design | Physical Design | Part 1 Understanding Low Power Design: Low power design is a collection of techniques and methods that help reduce the overall power consumption of an integrated circuit (IC). This includes both the dynamic and static power components. Think of it like this: when an IC is in use, it consumes power, and that power consumption can be broken down into two main categories - dynamic power and static power. Dynamic power is the power consumed when the IC is actively switching between different states, like when it's processing data or transmitting signals. Static power, on the other hand, is the power consumed even when the IC is idle, like when it's in standby mode. The goal of low power design is to minimize both dynamic and static power consumption, making the IC as energy-efficient as possible. This is super important for portable devices like smartphones, laptops, and wearables, where battery life is a major concern. Imagine being able to use...
    Read more

    PPA Optimization in Synthesis & Physical Design | Area | VLSI Design

    By
    In VLSI physical design and synthesis, achieving optimal PPA ( Power, Performance, Area)    is of paramount importance. Among these criteria, area efficiency is a critical consideration. EDA tools play a crucial role in optimizing area utilization hash  is of paramount importance. Among these criteria, area efficiency is a critical consideration. EDA tools play a crucial role in optimizing area utilization. Let's looks into various techniques for area optimization: Auto-Ungrouping & Boundary Optimization: hashtag EDA tools employ auto-ungrouping to strategically break down certain hierarchical structures, benefiting both area and timing. Furthermore, the tools optimize the placement of hierarchical instance boundaries to minimize area usage. It is recommended to keep these settings enabled, unless specific design constraints necessitate otherwise. Sequential Merging/Removal: EDA tools perform sequential analysis to identify and eliminate hashtag sequencial element...
    Read more

    Placement - Physical Design - Part 2 - General Setup

    By
    Dear Reader, In our previous vlogs, we looked into the fundamentals of placement flow and algorithms. Here is the link to access Part 1 of the placement vlogs: Understanding of Placement Physical . Before we discuss on a detailed exploration of placement algorithms, let's first address the setup requirements for the placement run. There are various setup and flow optimization settings available with EDA tools to explore, but let's focus on a few essential and mandatory setup requirements for the placement run. 1.Multiple Corner Optimization Setup: In today's design practices, it's crucial to account for multiple corners and assess timing in various scenarios. Therefore, it is imperative to optimize your design for multiple corners during the placement run. We should aim to optimize our design for all available setup corners while possibly excluding the hold corner. set_scenario_status <corner_for_setup> -active true 2. Physical Synthesis Netlist Setting: If you a...
    Read more

    Longer Routing Length | Tcl Scripting | Routing | Physical Design | VLSI

    By
    Longer Routing Length | Physical Design | Tcl Scripting In the routing stage of physical design, one of the most important sanity checks is to find out the length of the longer nets. However, EDA tools optimize the length of each net to meet its timing and DRC requirements. Despite their best efforts, EDA tools may not always optimize net lengths due to various reasons such as complexity of the design, limited visibility into the design's timing and signal integrity requirements, inadequate or incomplete design constraints, insufficient optimization algorithms or resources, and trade-offs between different design objectives. What is the impact of longer routing lengths on timing? Longer routing lengths lead to greater delay and can cause timing violations. To mitigate timing violations due to longer routing lengths, techniques such as layer promotion can be used, where the tool promotes the net to a higher metal layer based on needs and violations to meet the timing requirements....
    Read more