Understanding of Placement (Physical Design) - Part 1
In physical design, following floor-planning, the crucial step is placement, which heavily relies on the quality of the floorplan. Today, let's delve into placement algorithms.
Before commencing placement, conducting necessary checks called pre-placement checks is imperative. To ensure better timing quality, the following steps must be completed before initiating placement:
The above commands examine issues related to placement such as PG DRC, PG missing via, pin placement, grid, feedthrough issues, etc. Running these commands before placement aids in identifying major issues that could impede the placement process.
Different stages for the placement run include:
- 1.Initial coarse placement (initial_place)
- 2.High fanout buffering (initial_drc)
- 3.Initial optimization (initial_opto)
- 4.Final placement (final_place)
- 5.Final optimization (final_opto)
Each of these stages will be discussed in detail. All stages can be executed using the place_opt
command in Synopsys.
Additionally, each stage can be controlled using various control variables.
For instance, if during the placement run until the initial_drc
stage, there is significant congestion, the next steps depend on the severity of congestion. If the congestion is deemed unacceptable, there is no need to proceed to the next stage. Instead, analyse the congestion, revisit the unplaced design, refine and retune the recipe, and rerun the process.
All refinement and retuning can be controlled using variables. Therefore, understanding these variables is essential.
In the forthcoming blog, we will discuss the design and flow requirements, as well as quality of results (QoR) related setups necessary before initiating the placement process.
Happy Learning !
great job.
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