Longer Routing Length | Tcl Scripting | Routing | Physical Design | VLSI

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Longer Routing Length | Physical Design | Tcl Scripting

In the routing stage of physical design, one of the most important sanity checks is to find out the length of the longer nets. However, EDA tools optimize the length of each net to meet its timing and DRC requirements. Despite their best efforts, EDA tools may not always optimize net lengths due to various reasons such as complexity of the design, limited visibility into the design's timing and signal integrity requirements, inadequate or incomplete design constraints, insufficient optimization algorithms or resources, and trade-offs between different design objectives.

What is the impact of longer routing lengths on timing?

Longer routing lengths lead to greater delay and can cause timing violations. To mitigate timing violations due to longer routing lengths, techniques such as layer promotion can be used, where the tool promotes the net to a higher metal layer based on needs and violations to meet the timing requirements.

Why is it important for physical design engineers to report longer route lengths?

As a physical design engineer, it is important to report longer route lengths in the design and perform proper analysis to ensure that timing constraints are met. This can be done by writing a Tcl program to find the routing length of each net, for example, by defining a threshold length and iterating through each net to calculate its routing length.

How can we find the routing length of each net using a Tcl program?

The Tcl program can filter nets by metal layer, for instance, M2, and iterate through each net in the metal layer to calculate its routing length. 



# Define the threshold length (in microns)
set threshold_length 300

# Get all nets in the design
set nets [get_nets -all]

# Iterate through each net
foreach net $nets {
    # Get the net's routing length
    set route_length [get_attribute -net $net route_length]

    # Check if the route length exceeds the threshold
    if {$route_length > $threshold_length} {
        # Print the net name and route length
        puts "Net $net has a route length of $route_length um"
    }
}

# Filter nets by metal layer (e.g., M2)
set metal_layer "M2"
set metal_nets [get_nets -metal_layer $metal_layer]

# Iterate through each net in the metal layer
foreach net $metal_nets {
    # Get the net's routing length
    set route_length [get_route_length -net $net]

    # Check if the route length exceeds the threshold
    if {$route_length > $threshold_length} {
        # Print the net name and route length
        puts "Net $net in metal layer $metal_layer has a route length of $route_length um"
    }
}

What additional analysis should be performed based on the delay characteristics of each metal layer?

Proper analysis should be done based on the delay characteristics of each metal layer, taking into account how much delay will be introduced for a specific routing length.



Happy Learning !



#scripting #coding #Tcl #pd #physicaldesign #physicalverification #pv #vlsi #design #india #semiconductor #freshers #professional #hardware #floorplanning #motivation #leadership #magnet #bound #placement #synopsys #cadence #interview #vlsi #question #longer #routing #longnet #delay #timing #rc #resistance #capacitance

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  1. Kandula savithritailoring.blogspot.comNovember 6, 2024 at 4:20 AM


    set limit_length 300;
    set count 0
    set nets [get_nets * -hierarchical]
    foreach_in_collection net $nets {
    set net_name [get_object_name $net]
    set net_length [get_attribute $net dr_length]
    if { $net_length > $limit_length} {
    if { [get_attribute $net net_type] incr count== "signal" } {
    set route_length [get_attribute $net route_length]
    puts "$count : $net_name: $net_length : $route_length"
    }
    }
    }

    ReplyDelete

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