Port Punching | Physical Design | VLSI

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Port Punching in Physical Design VLSI:

Port punching refers to the process where a synthesis or implementation tool automatically creates a port to facilitate connections between hierarchical levels.

Let's understand this with a simple example. During the power planning stage, we use UPF commands like create_supply_net, create_supply_port, and connect_supply_net. These commands facilitate the addition of ports between hierarchical levels to establish supply connections, ensuring proper power distribution across the design.

Another example is feedthrough port punching/creation. In multi-voltage domains, many nets need to travel long distances due to multiple power domains. Since nets are not permitted to cross voltage areas to which they do not belong, this can lead to excessive wiring, congestion, and potential timing violations.

We can address these issues by breaking these nets using feedthroughs with extra ports created on the voltage area boundary, allowing nets to travel into different voltage areas with always-on buffering to solve timing issues.


With this approach, we achieve:

  •     Fewer routing resources
  •     Fewer buffers required

In brief, port punching is the process of defining and creating input and output ports on the periphery/hierarchy of the integrated circuit layout. These ports are essential for establishing connections. Port punching involves:

  •     Specifying location
  •     Specifying size
  •     Specifying type (input/output/bidirectional)
  •     Naming/labeling
  •     DRC rules compliance

Happy Learning !

#pd #ports #vlsi #pd #physicaldesign #verification #portpunching #power #semiconductor #freshers #infineon #india #timing #synthesis #implemtation #floorplan #placement #pv


Comments

  1. Nagendra Prasad NJanuary 9, 2025 at 2:44 AM

    can the tool optimization also cause port punching ? or should all of the port punching be present in the input upf ?

    ReplyDelete

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