LVS Issue | Physical verification | VLSI

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In Physical Design Verification / Layout Verification, one crucial process to ensure the manufacturability of chips is Layout vs Schematic (LVS). While other checks such as DRC, Antenna and Density issues are relatively easier to handle through scripting and custom approaches, LVS demands careful analysis and debugging.


In Simple word, LVS involves comparing the source netlist, which can be generated from a Verilog netlist (.v file) using v2lvs, with the layout netlist extracted from GDSII/Oasis files (.gds /.oas).

To ensure a smooth verification process and to get LVS smiley, certain tips should be followed:

Clean up open and short connections during the routing stage and fix any hierarchical shorts if detected. Power-related shorts and opens can be identified separately by running soft-check and ERC on the layout.

Ensure that the Base DRC is free from issues. Legalization problems like overlaps, missing fillers, or tap cells can lead to unnecessary LVS discrepancies.

When generating the source netlist, make sure to include a spice file for IP/Memory/Analog modules. Additionally, perform GDS merge with layout GDS for these hard IPs.

Verify that power-related settings are accurate. For hierarchical LVS comparison, exclude any modules that are not yet ready from the comparison process. To enable hierarchical comparison, include hcell to ensure each hierarchical module is evaluated independently.

After LVS comparison, the generated report may show discrepancies related to port mismatch, net mismatch, device mismatch, and connectivity issues.

By diligently addressing open and short connections, resolving Base DRC issues, and employing proper settings during the LVS process, designers can efficiently debug and fix LVS violations, leading to a successful chip layout verification and ultimately a functional chip.

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