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Physical Design Interview Question | VLSI Physical Design | Tcl Programming Let's say you are working on a block/partition and handling physical design tasks from floor-planning to final GDSII. Floor-planning is one of the major tasks, alongside power planning. Define the major tasks performed during floor-planning. What are the key considerations for both floor-planning and power planning? After completing the power planning, assume you encounter approximately 1000 power-ground (PG) shorts in the design on a specific layer, M1. How would you approach fixing these PG shorts? Additionally, write a program to quickly identify and resolve these shorts with built-in tool command. Company : Product Based Experience: 3+ Years Answer: Floor-planning: https://compile-vlsi.blogspot.com/2024/05/floorplan-series-part-1-physical-design.html https://compile-vlsi.blogspot.com/2024/05/floorplan-series-part-2-physical-design.html https://compile-vlsi.blogspot.com/2024/05/floor-planning-part-3-fin...

Lakhs of Base DRC at Floorplan/Placement database: Let's say you are working on one of the complex blocks of chip designing and you are responsible for closing the Place-and-Route (PnR) activity of the design. You are responsible for doing floor-planning, placement, clock tree synthesis, routing, and signoff activities. Floorplan is one of the most important tasks in physical design activities. One of the major tasks in floor-planning is macro placement, identification, and creation of physical power domains based on UPF, doing power planning including placement of physical cells like tap cells, boundary cells, power switches, guard rings, marker cells, and a few others. Let's say you completed the floor-planning and are ready to go for placement. Before going to the placement run, have you done sanity checks to ensure that your floorplan is completely clean and okay? For a sanity check with respect to physical violations, don't consider timing as of now to limit the discus...

Longer Routing Length | Physical Design | Tcl Scripting In the routing stage of physical design, one of the most important sanity checks is to find out the length of the longer nets. However, EDA tools optimize the length of each net to meet its timing and DRC requirements. Despite their best efforts, EDA tools may not always optimize net lengths due to various reasons such as complexity of the design, limited visibility into the design's timing and signal integrity requirements, inadequate or incomplete design constraints, insufficient optimization algorithms or resources, and trade-offs between different design objectives. What is the impact of longer routing lengths on timing? Longer routing lengths lead to greater delay and can cause timing violations. To mitigate timing violations due to longer routing lengths, techniques such as layer promotion can be used, where the tool promotes the net to a higher metal layer based on needs and violations to meet the timing requirements....

Scripting Interview Question 2 | Physical Design  | Floor-Planning | Tcl Programming Role:  Physical Design Company  : Product Based Experience:  5+ years Suppose you are working on floor-planning for a block-level implementation, and one of the key tasks is macro placement. In this scenario, there are special cells in the design that need to be placed according to specific requirements: The cells must be uniformly placed throughout the chip. The block has dimensions of 500 μm in height and 1000 μm in width. The distance between adjacent special cells should be 10 μm in both the vertical and horizontal directions. Each special cell has dimensions of 2 μm x 2 μm. The first special cell should be placed with an offset of 5 μm from the origin. Write a TCL script to implement this placement strategy at floorplan stage. Instructions for Submission: Please post your answers in the comment section below. For detailed explanations and solutions, check the answers later on...

Scripting Interview Question Role: Physical Design Company : Product Based Experience: 5+ years Write a program or suggest an algorithm that compares two files containing lines of code. The program should perform the following tasks: Consider all possible solutions and identify the most efficient one. Identify and report matching patterns between the two files. Identify and report non-matching patterns between the two files. Propose a solution for scenarios where the file sizes are small (hundreds of lines of code). Propose a solution for scenarios where the file sizes are large (thousands of lines of code). Discuss whether the same solution works for both small and large file sizes. Instructions for Submission: Please post your answers in the comment section below. For detailed explanations and solutions, check the answers later on compile-vlsi.blogspot.com Answer: (Updated on 01 Aug 2024) Approach 1: Brute Force Description: Use two nested loops to compare each line of the first f...

Write a Tcl program to find out unique/odd elements from the list 1,3,5,7,7,5,3,1,9. Input : 1,3,5,7,7,5,3,1,9 output : 9 While there are multiple ways to achieve this, as a hashtag VLSI engineer, we'll leverage the hashtag XOR operation. XOR (exclusive OR) results in 1 when two inputs are different and 0 when they are equal. In our program, every number appears twice except for 9. Therefore, by XOR-ing all elements in the list, the result will be 9, the unique/odd element. Below is Tcl Program: hashtag # Define the list set lst [list 1 3 5 3 1 5 9] hashtag # Initialize a variable to store the result set result 0 hashtag # iterate through the list and XOR all elements foreach num $lst { set result [expr {$result ^ $num}] } hashtag # The 'result' variable now contains the odd element puts "The odd element in the list is: $result" "This works well if we have a single unique element, but if there are two or more unique elements, a little extra effort is ...