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Physical Design Interview Question | VLSI Physical Design | Tcl Programming Let's say you are working on a block/partition and handling physical design tasks from floor-planning to final GDSII. Floor-planning is one of the major tasks, alongside power planning. Define the major tasks performed during floor-planning. What are the key considerations for both floor-planning and power planning? After completing the power planning, assume you encounter approximately 1000 power-ground (PG) shorts in the design on a specific layer, M1. How would you approach fixing these PG shorts? Additionally, write a program to quickly identify and resolve these shorts with built-in tool command. Company : Product Based Experience: 3+ Years Answer: Floor-planning: https://compile-vlsi.blogspot.com/2024/05/floorplan-series-part-1-physical-design.html https://compile-vlsi.blogspot.com/2024/05/floorplan-series-part-2-physical-design.html https://compile-vlsi.blogspot.com/2024/05/floor-planning-part-3-fin...

Lakhs of Base DRC at Floorplan/Placement database: Let's say you are working on one of the complex blocks of chip designing and you are responsible for closing the Place-and-Route (PnR) activity of the design. You are responsible for doing floor-planning, placement, clock tree synthesis, routing, and signoff activities. Floorplan is one of the most important tasks in physical design activities. One of the major tasks in floor-planning is macro placement, identification, and creation of physical power domains based on UPF, doing power planning including placement of physical cells like tap cells, boundary cells, power switches, guard rings, marker cells, and a few others. Let's say you completed the floor-planning and are ready to go for placement. Before going to the placement run, have you done sanity checks to ensure that your floorplan is completely clean and okay? For a sanity check with respect to physical violations, don't consider timing as of now to limit the discus...

Scripting Interview Question 2 | Physical Design  | Floor-Planning | Tcl Programming Role:  Physical Design Company  : Product Based Experience:  5+ years Suppose you are working on floor-planning for a block-level implementation, and one of the key tasks is macro placement. In this scenario, there are special cells in the design that need to be placed according to specific requirements: The cells must be uniformly placed throughout the chip. The block has dimensions of 500 μm in height and 1000 μm in width. The distance between adjacent special cells should be 10 μm in both the vertical and horizontal directions. Each special cell has dimensions of 2 μm x 2 μm. The first special cell should be placed with an offset of 5 μm from the origin. Write a TCL script to implement this placement strategy at floorplan stage. Instructions for Submission: Please post your answers in the comment section below. For detailed explanations and solutions, check the answers later on...

Scripting Interview Question Role: Physical Design Company : Product Based Experience: 5+ years Write a program or suggest an algorithm that compares two files containing lines of code. The program should perform the following tasks: Consider all possible solutions and identify the most efficient one. Identify and report matching patterns between the two files. Identify and report non-matching patterns between the two files. Propose a solution for scenarios where the file sizes are small (hundreds of lines of code). Propose a solution for scenarios where the file sizes are large (thousands of lines of code). Discuss whether the same solution works for both small and large file sizes. Instructions for Submission: Please post your answers in the comment section below. For detailed explanations and solutions, check the answers later on compile-vlsi.blogspot.com Answer: (Updated on 01 Aug 2024) Approach 1: Brute Force Description: Use two nested loops to compare each line of the first f...

In Physical Design Verification / Layout Verification, one crucial process to ensure the manufacturability of chips is Layout vs Schematic (LVS). While other checks such as DRC, Antenna and Density issues are relatively easier to handle through scripting and custom approaches, LVS demands careful analysis and debugging. In Simple word, LVS involves comparing the source netlist, which can be generated from a Verilog netlist (.v file) using v2lvs, with the layout netlist extracted from GDSII/Oasis files (.gds /.oas). To ensure a smooth verification process and to get LVS smiley, certain tips should be followed: Clean up open and short connections during the routing stage and fix any hierarchical shorts if detected. Power-related shorts and opens can be identified separately by running soft-check and ERC on the layout. Ensure that the Base DRC is free from issues. Legalization problems like overlaps, missing fillers, or tap cells can lead to unnecessary LVS discrepancies. When generating ...

Dealing with Congestion in a Practical Way (Physical Design): Simply put, if number of required track is more than available track in a specific GRC, the tool flags an overflow in that area. The tool breaks down the chip core into small GRCs (Global Route Cells) and assesses overflow, reporting it for horizontal, vertical, and both layers. Normally, the overflow percentage should stay below 1%, requiring analysis if it exceeds that. But what if it's significantly high, like 10-20%? Even with a high overflow, the tool routes, but at the expense of shorts and DRC violations, resulting in poor net quality. Long nets contribute to high RC values, causing more delays and eventually timing violations in design. Therefore, prioritizing congestion analysis is crucial. Let's look into potential causes of congestion/overflow: 1.Improper logic optimization during synthesis. 2.Bad floorplan (Check my post on floorplan for macro placements). https://lnkd.in/gU9PnZve 3.Incorrect standard ce...