Dealing with Congestion in a Practical Way (Physical Design) :

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Dealing with Congestion in a Practical Way (Physical Design):


Simply put, if number of required track is more than available track in a specific GRC, the tool flags an overflow in that area.


The tool breaks down the chip core into small GRCs (Global Route Cells) and assesses overflow, reporting it for horizontal, vertical, and both layers.


Normally, the overflow percentage should stay below 1%, requiring analysis if it exceeds that. But what if it's significantly high, like 10-20%?


Even with a high overflow, the tool routes, but at the expense of shorts and DRC violations, resulting in poor net quality. Long nets contribute to high RC values, causing more delays and eventually timing violations in design. Therefore, prioritizing congestion analysis is crucial.


Let's look into potential causes of congestion/overflow:


1.Improper logic optimization during synthesis.

2.Bad floorplan (Check my post on floorplan for macro placements).

https://lnkd.in/gU9PnZve

3.Incorrect standard cell placement in the placement stage.

4.High cell density.

5.High pin/port density.

6.Improper blockages during placement/floorplan.

7.Scan chain reordering disabled.

8.Criss-cross routing for high pin density cells like AOI.

9.Excessive addition of buffers/inv during hold fixing/optimization.



Having understood the causes, let's explore common practices to tackle congestion:


1.Prioritize analysis.

2.Implement Physical Aware Synthesis.

3.Ensure proper macro placement during floorplanning, considering channels and blockages.

4.Apply cell padding and keepout margins during placement.

5.Set appropriate placement blockages (soft, hard, partial) based on requirements.

6.Opt for congestion-driven placement with high effort.

7.Analyze cell density/pin density during placement.

8.Adjust cell density utilization for congested areas.

9.Enable scan reordering.

10.Conduct power grid analysis.


By incorporating these congestion-handling techniques, congestion can be effectively addressed.


Do Share your experiences in handling congestion in the comment section.


Happy Learning!


#pd #physicaldesign #physicalverification #semiconductor #designengineer #vlsi #infineon #chipdesign #congestion #placement

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