compile-vlsi

  Interview Question (PD): Consider a design that has undergone floor-planning, placement, Clock Tree Synthesis (CTS), and routing, complete Physical Design (PD) activity. After multiple iterations to fix timing, two runs have been generated: Run A with zero skew (practically not possible, but assume) and Run B with a skew of 50ps. Both runs meet the required timing specifications. Which run is the good one? Can we go ahead with the zero skew run, or should we opt for the run with some skew? What are the disadvantages of going with the zero skew run? In particular, are there any potential issues with the zero skew run that could lead to reliability or performance problems down the line? For example, might the zero skew run be more sensitive to process, voltage, and temperature (PVT) variations, IR drop or more prone to clock signal degradation? On the other hand, does the run with some skew provide a more realistic and robust clock distribution network that can better withstand va...

Magnet Placement and Placement Bound in  VLSI Physical Design These two popular techniques used to optimize placement are Placement Bounds and Magnet Placement. While both techniques aim to improve placement, they differ in their approach, application, and benefits. In this article, we'll look into the details of each technique and compare them to help designers make informed decisions. 1. Placement Bounds Placement Bounds are a type of constraint that controls the placement of groups of leaf cells and hierarchical cells. They allow designers to group cells to minimize wire length and place the cells at the most appropriate locations. Placement Bounds are particularly useful when timing is critical during placement, and cells need to be placed in close proximity to each other. Types of placement Bound: Soft Bound : A Soft Bound is a type of Placement Bound that suggests a preferred placement region for a group of cells. The placement tool tries to place the cells within the specifi...

Port Punching in Physical Design VLSI: Port punching refers to the process where a synthesis or implementation tool automatically creates a port to facilitate connections between hierarchical levels. Let's understand this with a simple example. During the power planning stage, we use UPF commands like create_supply_net, create_supply_port, and connect_supply_net. These commands facilitate the addition of ports between hierarchical levels to establish supply connections, ensuring proper power distribution across the design. Another example is feedthrough port punching/creation. In multi-voltage domains, many nets need to travel long distances due to multiple power domains. Since nets are not permitted to cross voltage areas to which they do not belong, this can lead to excessive wiring, congestion, and potential timing violations. We can address these issues by breaking these nets using feedthroughs with extra ports created on the voltage area boundary, allowing nets to travel into ...

In VLSI physical design and synthesis, achieving optimal PPA ( Power, Performance, Area)    is of paramount importance. Among these criteria, area efficiency is a critical consideration. EDA tools play a crucial role in optimizing area utilization hash  is of paramount importance. Among these criteria, area efficiency is a critical consideration. EDA tools play a crucial role in optimizing area utilization. Let's looks into various techniques for area optimization: Auto-Ungrouping & Boundary Optimization: hashtag EDA tools employ auto-ungrouping to strategically break down certain hierarchical structures, benefiting both area and timing. Furthermore, the tools optimize the placement of hierarchical instance boundaries to minimize area usage. It is recommended to keep these settings enabled, unless specific design constraints necessitate otherwise. Sequential Merging/Removal: EDA tools perform sequential analysis to identify and eliminate hashtag sequencial element...