Inputs to Physical Design with examples | VLSI

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Today, let's discuss the inputs required to start physical design, along with example.

1. Gate Level Netlist:

This is a representation of the circuit at the gate level. It defines the logic gates and their interconnections.

                    module and_gate (input A, input B, output Y);

                        assign Y = A & B;

                    endmodule


2. Cell Libraries:

Cell libraries contain information about the standard cells used in the design. There are different types of libraries:

  • Logical Library / timing libraries: Defines the logical functionality of the cells and  provides timing information (e.g., delays, setup, and hold times).
  • Physical Library: Contains physical dimensions and layout information of the cells.
If you are working with a Synopsys-based flow, you might encounter .db and .frame files. The .db files are logical libraries, while the .frame files are physical libraries. You can create a library based on the input .db and .frame files, as well as an .ndm file. Sometimes, for standard cells, we use the .ndm file, and for macro files, we use the .db and .frame files.

  • create_lib is command to create library using logical , physical , and technology library.

3. Technology Library:

This library contains information specific to the technology node, such as metal layers, via definitions, and design rules. It includes the technology file and RC model file (TLU+).

LAYER M1 {

    TYPE ROUTING ;

    DIRECTION HORIZONTAL ;

    PITCH 0.14 ;

    WIDTH 0.07 ;

    SPACING 0.07 ;

}

VIA V1 {

    LAYERS M1 CUT M2 ;

    RECT 0.07 0.07 0.14 0.14 ;

}


4. MCMM Timing Constraints

Multi-corner multi-mode (MCMM) timing constraints define the different operating conditions and modes for timing analysis.


> create_clock -name clk -period 10 [get_ports clk]

> set_input_delay -clock clk 2 [get_ports input]

> set_output_delay -clock clk 2 [get_ports output]


5. Power Intent UPF

Unified Power Format (UPF) file specifies the power intent of the design, including power domains and supply networks.


> create_power_domain PD1

> create_power_domain PD2

> create_supply_net VDD -domain PD1

> create_supply_net VSS -domain PD2


6.Floorplan DEF / IO Placement:

If you are working at the block level, you will receive the design boundary from the full chip team as well as an IO placement file.


7. Scan DEF

Scan DEF file defines the scan chain and its connections for Design for Testability (DFT).

NETS 1 ;

- scan_chain_1

  ( FF1 Q ) ( FF2 D ) ( FF2 Q ) ( FF3 D ) ;

END NETS ;


Summary:

  1. Read the netlist into the design environment.
  2. Load the cell libraries to get logical, timing, and physical data.
  3. Load the technology library for process-specific rules, including the technology file and RC model file (TLU+).
  4. Apply the timing constraints to guide the design timing.
  5. Specify the power intent using UPF.
  6. Create the floorplan by defining the chip layout.
  7. read scan chains for DFT.

Happy Learning !

#pd #physicaldesign #vlsi #india #semiconductor #input #cells #libraries #upf #power #drc #logical #physical 























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