Floorplan Series - Part 2 | Physical Design

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 Floorplan Series - Part 2 ....


In the previous post (https://lnkd.in/g2gEyGU4), we explored block-level floor-planning at an abstract level. Now, let's look into the detailed steps of this process.


Initial Floorplan:

Assuming the availability of an IO (input-output) placement file and block boundary information provided by the full-chip engineer, we move forward in the context of low-power design. Shaping the voltage area is a crucial step, aligned with the power domain defined in the UPF (Unified Power Format) file. This involves creating a corresponding voltage area, shaping it, and strategically placing Macros.


For the initial floorplan at the block level, a major focus lies on Macro/Memory placement. Some blocks might be dominated by macros or memory, allocating 70 to 80 percent of the area to these components. Others may have 20-30 percent Macros, leaving the rest for standard cell placement. It's imperative to follow guidelines during the placement of these macros.


1.Grouping macros is essential. Post-grouping, it becomes clear which macros belong to the same group. Macros that communicate with each other should be placed together, and fly-line analysis can facilitate this.


2.Macros should generally face towards the boundary of blocks, with pins directed towards interacting macros or the core of the design.


3.Minimum spacing between macros:

Ensure compliance with minimum spacing guidelines based on technology. If two macros do not communicate, they can be placed with minimum spacing or abut based on technology requirements. Utilize the following formula for a rough idea of channel spacing:

Channel Spacing=Number of Pins×Pitch×2/Metal Layer

Refine this spacing based on congestion considerations.


4.Introduce halos around macros to prevent congestion.


5.Wherever channels exist between macros, ensure the placement of hard/partial blockages. Use buffer-only blockages to optimize timing.


6.Avoid creating notches during macro placement to prevent congestion. If notches form, include hard blockages.


7.For macro-dominated blocks, while stacking/grouping macros vertically. Provide horizontal channels for buffer placement to avoid transition/hold issues later in the design.


There are few other guidelines to follow, particularly in low-node technology. Further exploration of guidelines and parameters will be discussed in the next part of this post.


Happy Learning!


#physicaldesign #semiconductor #designengineering #vlsidesign #infineon #eda #engineering #learning #development #leadership

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