Floorplan Series: Part 1 | Physical Design

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 Floorplan Series: Part 1


Understanding Floorplanning in VLSI Physical Design


In VLSI physical design, the floorplan is one of important task and initial task in the design. comprising two primary types: full chip floorplan and block-level floorplan.


The majority of professionals in the industry works in block-level floorplanning while a select few enginner with extensive expertise works for fullchip floorplanning.



Consider, a processor design partitioned into 10 sub-partitions, each sub-partition divided into 70 blocks/partition. Under a hierarchical floorplan, these sub-partitions further divide into blocks or partitions, enabling multiple engineers to work concurrently.


Let's discuss Block level floorplanning in details:


For block-level floorplans, crucial parameters such as IO placement and boundary size data are provided by full chip engineers.



Major tasks done by Block level engineer:


1.Placement of hard macros/memory.

2.Creation of voltage areas in low-power designs.

3.Power planning.

4.Placement of physical cells such as tap cells and boundary cells.

5.placement of special cells based on specific requirements.


Block-level floorplans are typically divided into two stages:


1. Initial Floorplan:


Voltage area creation

Macro placement

Special cell integration, including Electrostatic Discharge (ESD) and Marker cells, addresses unique design requirements.



2.Final Floorplan:


Power planning

Placement of physical cells like tap cells, and boundary cells.


Let's discuss these in details in upcoming post.


Please post your learning and experience in comment section.



Happy Learning!


#physical #vlsi #vlsidesign #learning #physicaldesign #semiconductor #design

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