Floor-planning - Part 3 - Final | Physical Design

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Floor-planning - Part 3 - Final

Latch-up, HV DRC, Physical cell placement, Power Planning


Generally, we emphasize timing perspective during floor-planning. It's crucial to equally prioritize Physical verification, particularly focusing on base DRC and High Voltage DRC. Identifying circuitry prone to latch-up and recommending fixes is essential. Traditional methods such as guard-ring and spacing play a vital role in addressing latch-up issues.


Floor-Planning Part 1:

https://lnkd.in/g2gEyGU4

Floor-Planning Part 2:

https://lnkd.in/gHYVQfT2


In low-power design, circuitry susceptible to latchup requires considerations like denser tap-cell requirements and specific placement guidelines, such as avoiding active circuitry around them based on technology. Integrating these placement guidelines during the floorplan stage allows for early latchup fixes in the design.


High voltage signals necessitate special routing requirements, such as double spacing. Allocating and reserving tracks for these signals at an early stage helps prevent congestion and high-voltage issues later on.


After Macro placement, EDA tools perform physical cell placement and power planning. The tool adds tap cells at regular intervals based on technology requirements and incorporates end cap cells/boundary cells around macros and at core boundaries to safeguard & DRC issues. Decap cells and special marker cells are also added as per design requirements.


Finally, the tool conducts power network synthesis, implementing power planning algorithms defined by technology requirements. Lower technology designs often exhibit more layers as part of the stripe compared to higher technology. As a physical design engineer, our role involves checking the robustness of power stripes and rails, ensuring the absence of missing vias, weak vias, and shorts in the design to address significant issues early on.


Common Command used:

shape_blocks

create_keepout_margin

create_placement_bloackage

check_pg_connectivity

get_attribute

set_attribute


get_db

set_db

check_power_vias


Happy Learning !


#technology #learning #floorplanning #power #vlsi #development #semiconductor #processor #optimization #scripting #infineon

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