Placement | Physical Design | Timing Setup | Part 4

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 Dear Readers,

In our previous vlogs, we looked into the fundamentals of placement flow and algorithms, as well as the general setup mandatory for placement runs as well as setup required for congestion, power and area specific.

Today we will look to timing related setup required for placement run.

Below are the links to access these blogs :

Placement - Part 1

https://compile-vlsi.blogspot.com/2024/03/understanding-of-placement-physical.html

Placement - Part 2

https://compile-vlsi.blogspot.com/2024/03/placement-physical-design-part-2.html

Placement - Part 3

https://compile-vlsi.blogspot.com/2024/04/placement-physical-design-part-3.html


Once congestion reaches an acceptable level, the next analysis will shift to timing and logical DRC.

Let's explore the setup requirements for timing improvement in the placement run step by step.


1.Effort Level: Increasing the placement effort level or timing effort level to high may enhance the timing quality of results (QoR). However, this improvement comes at the expense of runtime, area, or even power.

place_opt.initial_place.effort high place_opt.final_place.effort high opt.timing.effort high

 2.Stream Legalization:

Stream legalization options allow control over how far cells can be moved during legalization, which is particularly crucial in lower technologies to improve timing.

place.legalize.place.stream true

 

3.Create Cell Bound:

Placement bounds can constrain cell placement in specific regions, which is useful for placing timing-critical cells according to specific requirements.

create_bound -name <> -type <> -boundary <> <cell_list>

 

The cell bound may be soft, hard & exclusive.

 

 4.Path Group:

Creating paths for specific clocks or timing-critical paths and assigning weights ensures priority placement of these paths.


5. Cell Density Control:

By default, the tool evenly distributes cells to achieve optimal placement. However, we can control cell density using appropriate options to place cells more densely in congested regions, thereby reducing congestion.

    >place.coarse.auto_density_control true     >place.coarse.auto_density_control false     >place.coarse.max_density 0.7     >place.coarse.congestion_driven_max_util 0.93 

6.Clock Gating Path Fixing:

Fixing clock gating critical setup paths is vital, utilizing trial CTS, ICG splitting, and clock-aware placement for better guidance.

    >place.opt.flow.optimize_icgs true

Trial CTS provides better guidance for ICG cell splitting and clock aware placement. CTS setup is needed got trail CTS.

7.Path Optimization:

Identifying unbalanced registers that violate timing and optimizing paths by moving registers and buffers to take advantage of nearby slack.

8.Layer Promotion:

Promoting wires to higher layers effectively reduces delay and aids in fixing timing issues in the design.

Happy learning! #physicaldesign #vlsi #india #infineon #semiconductor #physicalverification #timing #sta #design #learning #development #jobs #freshers



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