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Low Power Design | Physical Design | Static & Dynamic Power | Leakage Current | Part 2 The goal of low power design is to reduce the individual components of power as much as possible, thereby reducing the overall power consumption. The power equation contains components for dynamic and static power. Dynamic power is comprised of switching and short-circuit power; whereas static power is comprised of leakage, or current that flows through the transistor when there is no activity.  The higher the voltage, the higher the power consumed by each component, resulting in higher overall power. Conversely, the lower the voltage, the lower the overall power. To achieve the best performance with the lowest power consumption, tradeoffs for each of these different factors are tried and tested via various low power techniques and methodologies. Static Power Consumption When a circuit is in a quiescent state, meaning there is no activity or clock signal, it still consumes power, known a...

Low Power Design | Physical Design | Part 1 Understanding Low Power Design: Low power design is a collection of techniques and methods that help reduce the overall power consumption of an integrated circuit (IC). This includes both the dynamic and static power components. Think of it like this: when an IC is in use, it consumes power, and that power consumption can be broken down into two main categories - dynamic power and static power. Dynamic power is the power consumed when the IC is actively switching between different states, like when it's processing data or transmitting signals. Static power, on the other hand, is the power consumed even when the IC is idle, like when it's in standby mode. The goal of low power design is to minimize both dynamic and static power consumption, making the IC as energy-efficient as possible. This is super important for portable devices like smartphones, laptops, and wearables, where battery life is a major concern. Imagine being able to use...

Lakhs of Base DRC at Floorplan/Placement database: Let's say you are working on one of the complex blocks of chip designing and you are responsible for closing the Place-and-Route (PnR) activity of the design. You are responsible for doing floor-planning, placement, clock tree synthesis, routing, and signoff activities. Floorplan is one of the most important tasks in physical design activities. One of the major tasks in floor-planning is macro placement, identification, and creation of physical power domains based on UPF, doing power planning including placement of physical cells like tap cells, boundary cells, power switches, guard rings, marker cells, and a few others. Let's say you completed the floor-planning and are ready to go for placement. Before going to the placement run, have you done sanity checks to ensure that your floorplan is completely clean and okay? For a sanity check with respect to physical violations, don't consider timing as of now to limit the discus...

Longer Routing Length | Physical Design | Tcl Scripting In the routing stage of physical design, one of the most important sanity checks is to find out the length of the longer nets. However, EDA tools optimize the length of each net to meet its timing and DRC requirements. Despite their best efforts, EDA tools may not always optimize net lengths due to various reasons such as complexity of the design, limited visibility into the design's timing and signal integrity requirements, inadequate or incomplete design constraints, insufficient optimization algorithms or resources, and trade-offs between different design objectives. What is the impact of longer routing lengths on timing? Longer routing lengths lead to greater delay and can cause timing violations. To mitigate timing violations due to longer routing lengths, techniques such as layer promotion can be used, where the tool promotes the net to a higher metal layer based on needs and violations to meet the timing requirements....

Power Switches in VLSI Design | Interview Question PD | Oct 1 2024 Question: What are the different power switches used in VLSI design? How do bulk power switches differ from distributed power switches? What is the importance of power switches in IR drop analysis? How do power switches handle current during the transition from off to on power domain? What is rush current, and how do power switches handle it? What is ramp-up time, and how is it related to power switches? Sub-questions: Types of Power Switches:  What are the different types of power switches used in VLSI design, and what are their characteristics?                                                                                                          ...

  Interview Question (PD): Consider a design that has undergone floor-planning, placement, Clock Tree Synthesis (CTS), and routing, complete Physical Design (PD) activity. After multiple iterations to fix timing, two runs have been generated: Run A with zero skew (practically not possible, but assume) and Run B with a skew of 50ps. Both runs meet the required timing specifications. Which run is the good one? Can we go ahead with the zero skew run, or should we opt for the run with some skew? What are the disadvantages of going with the zero skew run? In particular, are there any potential issues with the zero skew run that could lead to reliability or performance problems down the line? For example, might the zero skew run be more sensitive to process, voltage, and temperature (PVT) variations, IR drop or more prone to clock signal degradation? On the other hand, does the run with some skew provide a more realistic and robust clock distribution network that can better withstand va...

Magnet Placement and Placement Bound in  VLSI Physical Design These two popular techniques used to optimize placement are Placement Bounds and Magnet Placement. While both techniques aim to improve placement, they differ in their approach, application, and benefits. In this article, we'll look into the details of each technique and compare them to help designers make informed decisions. 1. Placement Bounds Placement Bounds are a type of constraint that controls the placement of groups of leaf cells and hierarchical cells. They allow designers to group cells to minimize wire length and place the cells at the most appropriate locations. Placement Bounds are particularly useful when timing is critical during placement, and cells need to be placed in close proximity to each other. Types of placement Bound: Soft Bound : A Soft Bound is a type of Placement Bound that suggests a preferred placement region for a group of cells. The placement tool tries to place the cells within the specifi...

Scripting Interview Question 2 | Physical Design  | Floor-Planning | Tcl Programming Role:  Physical Design Company  : Product Based Experience:  5+ years Suppose you are working on floor-planning for a block-level implementation, and one of the key tasks is macro placement. In this scenario, there are special cells in the design that need to be placed according to specific requirements: The cells must be uniformly placed throughout the chip. The block has dimensions of 500 μm in height and 1000 μm in width. The distance between adjacent special cells should be 10 μm in both the vertical and horizontal directions. Each special cell has dimensions of 2 μm x 2 μm. The first special cell should be placed with an offset of 5 μm from the origin. Write a TCL script to implement this placement strategy at floorplan stage. Instructions for Submission: Please post your answers in the comment section below. For detailed explanations and solutions, check the answers later on...

Scripting Interview Question Role: Physical Design Company : Product Based Experience: 5+ years Write a program or suggest an algorithm that compares two files containing lines of code. The program should perform the following tasks: Consider all possible solutions and identify the most efficient one. Identify and report matching patterns between the two files. Identify and report non-matching patterns between the two files. Propose a solution for scenarios where the file sizes are small (hundreds of lines of code). Propose a solution for scenarios where the file sizes are large (thousands of lines of code). Discuss whether the same solution works for both small and large file sizes. Instructions for Submission: Please post your answers in the comment section below. For detailed explanations and solutions, check the answers later on compile-vlsi.blogspot.com Answer: (Updated on 01 Aug 2024) Approach 1: Brute Force Description: Use two nested loops to compare each line of the first f...

Port Punching in Physical Design VLSI: Port punching refers to the process where a synthesis or implementation tool automatically creates a port to facilitate connections between hierarchical levels. Let's understand this with a simple example. During the power planning stage, we use UPF commands like create_supply_net, create_supply_port, and connect_supply_net. These commands facilitate the addition of ports between hierarchical levels to establish supply connections, ensuring proper power distribution across the design. Another example is feedthrough port punching/creation. In multi-voltage domains, many nets need to travel long distances due to multiple power domains. Since nets are not permitted to cross voltage areas to which they do not belong, this can lead to excessive wiring, congestion, and potential timing violations. We can address these issues by breaking these nets using feedthroughs with extra ports created on the voltage area boundary, allowing nets to travel into ...