compile-vlsi

  Floorplan Series - Part 2 .... In the previous post (https://lnkd.in/g2gEyGU4), we explored block-level floor-planning at an abstract level. Now, let's look into the detailed steps of this process. Initial Floorplan: Assuming the availability of an IO (input-output) placement file and block boundary information provided by the full-chip engineer, we move forward in the context of low-power design. Shaping the voltage area is a crucial step, aligned with the power domain defined in the UPF (Unified Power Format) file. This involves creating a corresponding voltage area, shaping it, and strategically placing Macros. For the initial floorplan at the block level, a major focus lies on Macro/Memory placement. Some blocks might be dominated by macros or memory, allocating 70 to 80 percent of the area to these components. Others may have 20-30 percent Macros, leaving the rest for standard cell placement. It's imperative to follow guidelines during the placement of these macros. 1.Gr...

  Floorplan Series: Part 1 Understanding Floorplanning in VLSI Physical Design In VLSI physical design, the floorplan is one of important task and initial task in the design. comprising two primary types: full chip floorplan and block-level floorplan. The majority of professionals in the industry works in block-level floorplanning while a select few enginner with extensive expertise works for fullchip floorplanning. Consider, a processor design partitioned into 10 sub-partitions, each sub-partition divided into 70 blocks/partition. Under a hierarchical floorplan, these sub-partitions further divide into blocks or partitions, enabling multiple engineers to work concurrently. Let's discuss Block level floorplanning in details: For block-level floorplans, crucial parameters such as IO placement and boundary size data are provided by full chip engineers. Major tasks done by Block level engineer: 1.Placement of hard macros/memory. 2.Creation of voltage areas in low-power designs. 3.P...

Dealing with Congestion in a Practical Way (Physical Design): Simply put, if number of required track is more than available track in a specific GRC, the tool flags an overflow in that area. The tool breaks down the chip core into small GRCs (Global Route Cells) and assesses overflow, reporting it for horizontal, vertical, and both layers. Normally, the overflow percentage should stay below 1%, requiring analysis if it exceeds that. But what if it's significantly high, like 10-20%? Even with a high overflow, the tool routes, but at the expense of shorts and DRC violations, resulting in poor net quality. Long nets contribute to high RC values, causing more delays and eventually timing violations in design. Therefore, prioritizing congestion analysis is crucial. Let's look into potential causes of congestion/overflow: 1.Improper logic optimization during synthesis. 2.Bad floorplan (Check my post on floorplan for macro placements). https://lnkd.in/gU9PnZve 3.Incorrect standard ce...