compile-vlsi

Scripting Interview Question Role: Physical Design Company : Product Based Experience: 5+ years Write a program or suggest an algorithm that compares two files containing lines of code. The program should perform the following tasks: Consider all possible solutions and identify the most efficient one. Identify and report matching patterns between the two files. Identify and report non-matching patterns between the two files. Propose a solution for scenarios where the file sizes are small (hundreds of lines of code). Propose a solution for scenarios where the file sizes are large (thousands of lines of code). Discuss whether the same solution works for both small and large file sizes. Instructions for Submission: Please post your answers in the comment section below. For detailed explanations and solutions, check the answers later on compile-vlsi.blogspot.com Answer: (Updated on 01 Aug 2024) Approach 1: Brute Force Description: Use two nested loops to compare each line of the first f...

Port Punching in Physical Design VLSI: Port punching refers to the process where a synthesis or implementation tool automatically creates a port to facilitate connections between hierarchical levels. Let's understand this with a simple example. During the power planning stage, we use UPF commands like create_supply_net, create_supply_port, and connect_supply_net. These commands facilitate the addition of ports between hierarchical levels to establish supply connections, ensuring proper power distribution across the design. Another example is feedthrough port punching/creation. In multi-voltage domains, many nets need to travel long distances due to multiple power domains. Since nets are not permitted to cross voltage areas to which they do not belong, this can lead to excessive wiring, congestion, and potential timing violations. We can address these issues by breaking these nets using feedthroughs with extra ports created on the voltage area boundary, allowing nets to travel into ...

Inputs to Physical Design | VLSI Today, let's discuss the inputs required to start physical design, along with example. 1. Gate Level Netlist: This is a representation of the circuit at the gate level. It defines the logic gates and their interconnections.                          module and_gate (input A, input B, output Y);                              assign Y = A & B;                          endmodule 2. Cell Libraries: Cell libraries contain information about the standard cells used in the design. There are different types of libraries: Logical Library / timing libraries : Defines the logical functionality of the cells and  provides timing information (e.g., delays, setup, and hold times). Physical Library : Contains physical dimensions and ...