compile-vlsi

In the Physical Design/Implementation stage of chip design, we address both timing and transition violations. Let's assume the timing violations have been resolved in all corners, but a few transition violations remain to be fixed. Despite having a clean timing analysis, it is still necessary to address these transition violations. Transition violations are associated with rise and fall times, and it is crucial to meet the targeted limits to ensure the proper functioning of the chip. Even if a path meets timing requirements with a transition violation, it may only have a small margin. Such paths are susceptible to being affected by random process variations, which can result in functional and timing failures.  Now, let's explore practical methods to fix these violations. In the design flow, EDA tools often prioritize logical design rule check (DRC) fixes over maximum delay considerations. However, it is possible to modify this priority based on design analysis and requirements....

In Physical Design Verification / Layout Verification, one crucial process to ensure the manufacturability of chips is Layout vs Schematic (LVS). While other checks such as DRC, Antenna and Density issues are relatively easier to handle through scripting and custom approaches, LVS demands careful analysis and debugging. In Simple word, LVS involves comparing the source netlist, which can be generated from a Verilog netlist (.v file) using v2lvs, with the layout netlist extracted from GDSII/Oasis files (.gds /.oas). To ensure a smooth verification process and to get LVS smiley, certain tips should be followed: Clean up open and short connections during the routing stage and fix any hierarchical shorts if detected. Power-related shorts and opens can be identified separately by running soft-check and ERC on the layout. Ensure that the Base DRC is free from issues. Legalization problems like overlaps, missing fillers, or tap cells can lead to unnecessary LVS discrepancies. When generating ...

Floor-planning - Part 3 - Final Latch-up, HV DRC, Physical cell placement, Power Planning Generally, we emphasize timing perspective during floor-planning. It's crucial to equally prioritize Physical verification, particularly focusing on base DRC and High Voltage DRC. Identifying circuitry prone to latch-up and recommending fixes is essential. Traditional methods such as guard-ring and spacing play a vital role in addressing latch-up issues. Floor-Planning Part 1: https://lnkd.in/g2gEyGU4 Floor-Planning Part 2: https://lnkd.in/gHYVQfT2 In low-power design, circuitry susceptible to latchup requires considerations like denser tap-cell requirements and specific placement guidelines, such as avoiding active circuitry around them based on technology. Integrating these placement guidelines during the floorplan stage allows for early latchup fixes in the design. High voltage signals necessitate special routing requirements, such as double spacing. Allocating and reserving tracks for thes...