compile-vlsi

Dear Reader, In our previous vlogs, we looked into the fundamentals of placement flow and algorithms. Here is the link to access Part 1 of the placement vlogs: Understanding of Placement Physical . Before we discuss on a detailed exploration of placement algorithms, let's first address the setup requirements for the placement run. There are various setup and flow optimization settings available with EDA tools to explore, but let's focus on a few essential and mandatory setup requirements for the placement run. 1.Multiple Corner Optimization Setup: In today's design practices, it's crucial to account for multiple corners and assess timing in various scenarios. Therefore, it is imperative to optimize your design for multiple corners during the placement run. We should aim to optimize our design for all available setup corners while possibly excluding the hold corner. set_scenario_status <corner_for_setup> -active true 2. Physical Synthesis Netlist Setting: If you a...

In physical design, following floor-planning, the crucial step is placement, which heavily relies on the quality of the floorplan. Today, let's delve into placement algorithms. Before commencing placement, conducting necessary checks called pre-placement checks is imperative. To ensure better timing quality, the following steps must be completed before initiating placement: 1.Physical synthesis must be completed. so we can use coarse placement in placement stage.       2. EDA tool offers command to check for pre-placement issue. >check_design -checks pre_placement_stage (synopsys command) >check_design -type place -out_file pre_place_checks.tcl (cadence command) The above commands examine issues related to placement such as PG DRC, PG missing via, pin placement, grid, feedthrough issues, etc. Running these commands before placement aids in identifying major issues that could impede the placement process. Different stages for the placement run ...